Open Source Chip Design - Digital FPGA and ASIC flow

At the webinar 31. october 2022 hosted by Rolf and IDA fremtidsteknologi, Jørgen gave a 1 hour intro to Open Source Chip Design and promised to follow up with a handson workshop.  

This is the workshop where you can try out the tools and flow on your own labtop and your own designs. We will only do Open Source Digital FPGA and ASIC flows.  

We will start by installing tools and PDK on Linux or Linux for windows subsystem.  

We will then do an in depth walk through from HDL (Verilog/VHDL) to GDSII and learn what each intermidiate step does to the design.   

Basic understandings of how digital logic works would be good - but if you have expericience as data sciencetist or from programming you will still have potential to be come a chip designer or learn how to accelerate you algorithmes on FPGA and ASIC hardware. 

One week before the workshop, there will be send out a preperation mail with practical info on how to install tools and PDK.  

There will be served sandwitch and softdrinks during breaks.

Workshop will be led by Jørgen Kragh Jakobsen. Jørgen has 25 years of expericence as Chip designer and was part of the startup Merus Audio that have sold millions of chips to the esablished audio industri. 

For the last 1.5 year, Jørgen has worked as a consultant and been active in the open source chip design ecosystem.